1. Field of the Invention
This invention relates to input/output (I/O) circuits for integrated circuit (IC) devices, and more particularly, to an I/O circuit with a high I/O voltage tolerance.
2. Description of Related Art
An integrated circuit (IC) device is capable of holding a very great number of circuit components, including resistors, capacitors, and transistors, in a very small semiconductor chip made of silicon or gallium arsenide. An IC chip is typically 1 cm.sup.2 to 2 cm.sup.2 in size and 1 mm in thickness.
An IC device is composed of various conductive, semiconductive, and insulative components. In a metal-oxide semiconductor (MOS) IC device, when a voltage is applied to the conductive and semiconductive layers, a certain amount of electric charges accumulates at the PN junctions. When the applied voltage is increased to a certain level (called threshold voltage), it causes type inversion to some semiconductor components in the MOS IC device, i.e., P-type layers are inverted to N-type, and N-type layers are inverted to P-type. If the MOS IC device is of the type that has a pair of semiconductor regions on both sides of each data-storage capacitor in the MOS IC device and these regions are opposite in type to the associated MOS transistor, the type inversion of these regions cause them to be electrically connected.
Moreover, when the voltage applied to an IC device further exceeds a certain level (called breakdown voltage), it causes the IC device to break down, and even causes damage to the PN junctions and gate oxide of the MOS transistors in the IC device, thus leading to the occurrence of leakage current. It can even cause the IC device to burn down if the voltage exceeds the breakdown voltage by too much.
In IC device operating on two system voltages, for example 3.3 V and 5 V, and the 3.3 V circuitry and the 5 V circuitry share a common bus. Then, when the bus is used to transfer 5 V logic signals, it can cause stress to the 3.3 V circuitry, and thus is likely to cause damage to the PN junctions and gate oxides of the MOS transistors in the 3.3 V circuitry.
One solution to the foregoing problem is to use what is known as Dual Gate-Oxide technology, which can help increase the breakdown voltage and the time-dependent dielectric breakdown (TDDB) characteristic of the MOS transistors in the IC device. The TDDB characteristic is related to the reliability of the resulting IC device. One drawback to the Dual Gate Oxide technology, however, is that it is more costly to implement than the Single Gate-Oxide technology, approximately by 15%.
One solution to the foregoing problem is disclosed in U.S. Pat. No. 5,381,062 to AT&T, entitled "MULTI-VOLTAGE COMPATIBLE BIDIRECTIONAL BUFFER", and whose basic circuit configuration is illustrated in FIG. 1. As shown, this patented I/O circuit includes an I/O pad 10, a first PMOS transistor 11, a second PMOS transistor 12, a first NMOS transistor 13, and a second NMOS transistor 14. The first PMOS transistor 11 is connected in such a manner that its gate is connected to a first node 15 which is further connected to a first driver (not shown) for control of the ON/OFF state of the first PMOS transistor 11, while the second NMOS transistor 14 is connected in such a manner that its gate is connected to a second node 16 which is further connected to a second driver (not shown) for control of the ON/OFF state of the second NMOS transistor 14.
The I/O pad 10 is coupled to an output port of a 5 V IC device (not shown) for receiving a 5V system voltage therefrom. At output enable when the 5V system voltage is being input to the I/O pad 10, the sourcing of the 5 V system voltage is directed through the first and second PMOS transistors 11, 12, while the sinking of the same is directed through the first and second NMOS transistors 13, 14. The ON/OFF state of the first PMOS 11 is controlled by a first gate voltage signal applied by the first driver (not shown) to the node 15, while the ON/OFF state of the second NMOS 14 is controlled by a second gate voltage signal applied by the second driver (not shown) to the node 16. The I/O circuit of FIG. 1 can provide a reliable oxide layer and no leakage current in the PMOS transistors 11, 12 and thus can protect the 3.3 V circuitry from the 5 V system voltage.
One drawback to the foregoing I/O circuit of FIG. 1, however, is that the particular configuration of the PMOS transistors 11, 12 and the NMOS transistors 13, 14 makes the output impedance of the I/O circuit considerably higher, thus causing the signal transmission speed to be undesirably slow.
FIG. 2 shows another conventional I/O circuit, which is disclosed in U.S. Pat. No. 5,546,019 to TSMC (Taiwan Semiconductor Manufacture Corporation), entitled "CMOS I/O CIRCUIT WITH 3.3 V OUTPUT AND TOLERANCE OF 5 V INPUT". As shown, this patented I/O circuit includes an I/O pad 20, a pull-up circuit 21, a PMOS transistor 22, a pair of NMOS transistors 23, 24, and a control unit 25. The control unit 25 is used to control the ON/OFF states of the PMOS transistor 22 and the two NMOS transistors 23, 24. The particular configuration of the foregoing I/O circuit of FIG. 2 can help eliminate the problems of forward bias at the PN junction of the PMOS transistor 22 and achieve full swing by means of the pull-up circuit 21.
One drawback to the foregoing I/O circuit of FIG. 2, however, is that when the I/O circuit operates in high-impedance state, the input of the 5 V system voltage to the I/O pad 20 causes stress to the gate oxide of the NMOS transistor 24, which may make the I/O circuit unreliable to operate.
FIG. 3 shows the circuit structure of an input-stage circuit used in conventional I/O circuit, which is disclosed in U.S. Pat. No. 5,418,476 entitled "LOW VOLTAGE OUTPUT BUFFER WITH IMPROVED SPEED". As shown, the input-stage circuit includes an I/O pad 26, a PMOS transistor 27 and a pair of NMOS transistors 28, 29. In accordance with this patent, the NMOS transistor 28 is specifically arranged for the purpose of isolating the gate oxide of the NMOS transistor 29 from the I/O pad 26. When the 5 V system voltage is being input to the I/O pad 26, however, the voltage at the node G is V.sub.CC -V.sub.tN34, where V.sub.tN34 is the threshold voltage of the NMOS transistor 28, which is insufficient to switch the NMOS transistor 29 on and the NMOS transistor 27 off, thus leading to the occurrence of a DC leakage current to flow through the PMOS transistor 27 and the NMOS transistor 29 to the ground, as indicated by the arrow 18 in FIG. 3. This DC leakage current undesirably increases the power consumption of the associated I/O circuit.
In conclusion, conventional I/O circuits have the following drawbacks:
(1) First, in the prior art of FIG. 1, the sourcing and sinking of the received system voltage are directed through the first and second PMOS transistors 11, 12 and the first and second NMOS transistors 13, 14, which causes an increase to the output impedance of the I/O circuit and thus a decrease in the signal transmission speed via the I/O circuit. PA1 (2) Second, in the prior art of FIG. 2, the input of the 5 V system voltage to the I/O pad 20 when the I/O circuit operates in a high-impedance state causes stress to the gate oxide of the NMOS transistor 24, thus making the I/O circuit unreliable. PA1 (3) Third, in an I/O circuit with the input-stage circuit shown in FIG. 3, a DC leakage current 18 occurs since the provision of the NMOS transistor 28 causes an insufficient gate voltage to switch on the NMOS transistor 29 and concurrently switch off the PMOS transistor 27, thus resulting in a high power consumption.